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Digital I/O Boards
Digital I/O Boards

        General Standards Corporation is a leading supplier of high speed digital/parallel I/O boards for embedded applications on several form factors/busses, cable transceiver options, and for many operating systems.

        Cable transceiver options are RS-422, RS-485, LVDS, PECL, and TTL.

    Form factors: PCI-Express, PMC, PC/104-Plus, PC/104-Express, VME, CCPMC, XMC, PCI, PCI-X, cPCI, and cPCI-X. View our large variety of PMC adapters

    Software drivers: Windows, Linux, VxWorks, MathWorks Simulink & xPC Target, Labview, QNX, etc.

    Free Windows, Linux, and Labview Drivers.
    Free loaner boards.

Digital I/O Selection Table

Various I/O cables are available:
[View a list of cables, part numbers, and price]

To view our large variety of PMC adapters Click Here.

Free Drivers & Loaner Boards.
Software Driver Support.
  New: Conduction Cooled PMC (CCPMC)

  Coming Soon: XMC and PC/104-Express

    Applications include: sonar, battery monitoring, voice digitizing, precision instrumentation, noise monitoring, and sona-buoys, etc.

  For Info on Digital I/O Technology:
        RS-422 Transceiver Spec
        RS-485 Transceiver Spec
        Low-voltage differential signaling (LVDS)
        Positive emitter-coupled logic (PECL)
        Emitter-coupled logic (ECL)
        Transistor–Transistor Logic (TTL)

            RS-422 Transceiver Specification

    RS-422 is an American national standard ANSI/TIA/EIA-422-B (formerly RS-422) and its international equivalent ITU-T Recommendation V.11 (also known as X.27), are technical standards that specify the "electrical characteristics of the balanced voltage digital interface circuit"[1]. It provides for data transmission, using balanced or differential signaling, with unidirectional/non-reversible, terminated or non-terminated transmission lines, point to point, or multi-drop. In contrast to RS-485 (which is multi-point instead of multi-drop), EIA-422/V.11 does not allow multiple drivers but only multiple receivers.
    The current title of the ANSI standard is TIA-422 Electrical Characteristics of Balanced Voltage Differential Interface Circuits and is now in revision B, published in May 1994, and was reaffirmed by the Telecommunications Industry Association in 2005.
    Several key advantages offered by this standard include the differential receiver, a differential driver and data rates as high as 10 megabaud at 12 metres (40 ft). The specification itself does not set an upper limit on data rate, but rather shows how signal rate degrades with cable length. The figure plotting this stops at 10 Mbit/s.
    EIA-422 only specifies the electrical signaling characteristics of a single balanced signal. Protocols and pin assignments are defined in other specifications. The mechanical connections for this interface are specified by EIA-530 (DB-25 connector) or EIA-449 (DC-37 connector), however devices exist which have 4 screw-posts to implement the transmit and receive pair only. The maximum cable length is 1200 m. Maximum data rates are 10 Mbit/s at 12 m or 100 kbit/s at 1200 m. EIA-422 cannot implement a truly multi-point communications network (such as with EIA-485), however one driver can be connected to up to ten receivers. [Read more]

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            RS-485 Transceiver Specification

    EIA-485 (formerly RS-485 or RS485) is an OSI model physical layer electrical specification of a two-wire,[1] half-duplex, multipoint serial at 1200 m). Since it uses a differential balanced line over twisted pair (like EIA-422), it can span relatively large distances (up to 4000 feet or just over 1200 metres).
    In contrast to EIA-422, which has a single driver circuit which cannot be switched off, EIA-485 drivers need to be put in transmit mode explicitly by asserting a signal to the driver. This allows EIA-485 to implement linear topologies using only two wires. The equipment located along a set of EIA-485 wires are interchangeably called nodes, stations and devices.
    The recommended arrangement of the wires is as a connected series of point-to-point (multidropped) nodes, a line or bus, not a star, ring, or multiply-connected network. Ideally, the two ends of the cable will have a termination resistor connected across the two wires. Without termination resistors, reflections of fast driver edges can cause multiple data edges that can cause data corruption. Termination resistors also reduce electrical noise sensitivity due to the lower impedance, and bias resistors (see below) are required. The value of each termination resistor should be equal to the cable impedance (typically, 120 ohms for twisted pairs). Star and ring topologies are not recommended because of signal reflections or excessively low or high termination impedance.
    Somewhere along the set of wires, powered resistors are established to bias each data line/wire when the lines are not being driven by any device. This way, the lines will be biased to known voltages and nodes will not interpret the noise from undriven lines as actual data; without biasing resistors, the data lines float in such a way that electrical noise sensitivity is greatest when all device stations are silent or unpowered.
    Often in a master-slave arrangement when one device dubbed "the master" initiates all communication activity, the master device itself provides the bias and not the slave devices. In this configuration, the master device is typically centrally located along the set of EIA-485 wires, so it would be two slave devices located at the physical end of the wires that would provide the termination. The master device would provide termination if it itself was located at a physical end of the wires, but that is often a bad design as the master would be better located at a halfway point between the slave devices. Note that it is not a good idea to apply the bias at multiple node locations, because, by doing so, the effective bias resistance is lowered, which could possibly cause a violation of the EIA-485 specification and cause communications to malfunction. By keeping the biasing with the master, slave device design is simplified and this situation is avoided. [Read more]

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            Low-voltage differential signaling (LVDS)

    Low-voltage differential signaling, or LVDS, is an electrical signaling system that can run at very high speeds over cheap, twisted-pair copper cables. It was introduced in 1994, and has since become very popular in computers, where it forms part of very high-speed networks and computer buses.

                        Differential vs. Single-Ended Signaling
      LVDS is a differential signaling system, which means that it transmits two different voltages which are compared at the receiver. LVDS uses this difference in voltage between the two wires to encode the information. The transmitter injects a small current, nominally 3.5 mA, into one wire or the other, depending on the logic level to be sent. The current passes through a resistor of about 100 to 120 ? (matched to the characteristic impedance of the cable) at the receiving end, then returns in the opposite direction along the other wire. From Ohm's law, the voltage difference across the resistor is therefore about 350 mV. The receiver senses the polarity of this voltage to determine the logic level. This type of signalling is called a current loop.
    The small amplitude of the signal and the tight electric- and magnetic-field coupling between the two wires reduces the amount of radiated electromagnetic noise.
    The low common-mode voltage (the average of the voltages on the two wires) of about 1.25 V allows LVDS to be used with a wide range of integrated circuits with power supply voltages down to 2.5 V or lower. The low differential voltage, about 350 mV as stated above, causes LVDS to consume very little power compared to other systems. For example, the static power dissipation in the LVDS load resistor is 1.2 mW, compared to the 90 mW dissipated by the load resistor for an RS-422 signal. Without a load resistor the whole wire has to be loaded and unloaded for every bit of data. Using high frequencies and a load resistor so that a single bit only covers a part of the wire (while traveling near light speed) is more power efficient.
      LVDS is not the only differential signaling system in use. See Differential signaling for a list of other differential signalling systems. LVDS is currently the only scheme that combines low power dissipation with high speed.

      LVDS became popular in the latter half of the 1990s. Before that, computers were too slow to make use of such fast data rates, and the need to run twice as many wires for the same amount of data outweighed the speed benefits. Yet multimedia and supercomputer users, both of whom needed to move large amounts of data over links several meters long (from a disk drive to a workstation, for instance) maintained a widespread interest in LVDS.
      Two examples of LVDS use in computer buses come from HyperTransport and FireWire, both of which trace their ancestry back to the post-Futurebus work which also led to SCI. LVDS is supported in SCSI standards (Ultra-2 SCSI and later) to allow higher data rates and longer cable lengths. Serial ATA, RapidIO, and SpaceWire utilize LVDS to allow high speed data transfer.
      LVDS can also transport video data from graphics adapters to computer monitors, particularly flat panels, using the Flat Panel Display Link (FPD-Link), LVDS Display Interface (LDI), or OpenLDI standards. These standards allow a maximum pixel clock of 112 MHz, which suffices for a display resolution of 1400 x 1050 (SXGA+) at 60 Hz refresh. A dual link can boost the maximum display resolution to 2048 x 1536 (QXGA) at 60 Hz. FPD-Link works with cable lengths up to about 5 m, and LDI extends this to about 10 m.

          Comparison with parallel transmission
      LVDS is often used for serial data transmission, which involves sending data bit-by-bit down a single pair of wires. This is in contrast to conventional parallel transmission, in which several wires are used with a common ground to carry several signals at once. The high speed of LVDS, and its use of in-channel synchronisation, allows more data to be sent using fewer wires than can be done with a normal parallel bus. The device for converting between serial and parallel data is called a serializer/deserializer, abbreviated to SerDes.

          Multipoint LVDS
      When serial data transmission is not fast enough, data can be transmitted in parallel form using an LVDS pair for each bit or even byte (as in PCI Express or HyperTransport). This system is called bus LVDS, or BLVDS. Standard LVDS transmitters are designed for point-to-point links, but multipoint bus systems can be made using modified LVDS transmitters with high-current outputs that can drive multiple termination resistors. Bus LVDS and LVDM (by TI) are de facto multipoint LVDS standards. Multipoint LVDS (MLVDS) is the TIA standard (TIA-899) that has evolved and is used in AdvancedTCA for some clock distribution.
    MLVDS has two types of receivers. Type-1 are nearly compatible with LVDS and use a 0 Volt threshold. Type-2 use a 100 mV threshold to handle in a consistent way various errors such as open and short circuits. For MLVDS:

Input Min/Max Output Common Mode Min/Max Output Amplitude Min/Max
-1.4 / 3.8 V 0.3 / 2.1 V 0.480 / 0.650 V

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            Positive emitter-coupled logic (PECL)

    Positive emitter-coupled logic, or PECL, is a further development of the emitter-coupled logic (ECL) technology and requires a positive 5V supply instead of a negative 5V supply. The Low-voltage positive emitter-coupled logic (LVPECL) is an improved version of PECL to meet lower voltage requirements. PECL is a differential signaling system and mainly used in high speed and clock distribution circuits.

Logic Levels:

Vee Vlow Vhigh Vcc
GND 2.2 V 3.0 V 5.0 V

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            Emitter-coupled logic (ECL)

      Motorola ECL 10,000 basic gate circuit diagram[1]In electronics, emitter-coupled logic, or ECL, is a logic family in which current is steered through bipolar transistors to implement logic functions. ECL is sometimes called current-mode logic[2] or current-switch emitter-follower (CSEF) logic.[3][4]
    The chief characteristic of ECL is that the transistors are never in the saturation region and can thus change states at very high speed. Its major disadvantage is that the circuit continuously draws current, which means it requires a lot of power.

      Yourke's current switch, c. 1955.[5]ECL was invented in August 1956 at IBM by Hannon S. Yourke[6]. Originally called current steering logic, it was used in the Stretch, IBM 7090, and IBM 7094 computers.[5]
    While ECL circuits in the mid-1960s through the 1990s consisted of a differential amplifier input stage to perform logic, followed by an emitter follower to drive outputs and shift the output voltages so they will be compatible with the inputs, Yourke's current switch, also known as ECL, consisted only of differential amplifiers. To provide compatible input and output levels, two complementary versions were used, an NPN version and a PNP version. The NPN output could drive PNP inputs, and vice-versa. "The disadvantages are that more different power supply voltages are needed, and both pnp and npn transistors are required."[5]
    Motorola introduced their first digital monolithic integrated circuit line, MECL I, in 1962.[7]

    TTL and related families use transistors as digital switches where transistors are either cut off or saturated, depending on the state of the circuit. ECL gates use differential amplifier configurations at the input stage. A bias configuration supplies a constant voltage at the midrange of the low and high logic levels to the differential amplifier, so that the appropriate logical function of the input voltages will control the amplifier and the base of the output transistor (this output transistor is used in common collector configuration). The propagation time for this arrangement can be less than a nanosecond, making it for many years the fastest logic family.

    Other noteworthy characteristics of the ECL family include the fact that the large current requirement is approximately constant, and does not depend significantly on the state of the circuit. This means that ECL circuits generate relatively little power noise, unlike many other logic types which typically draw far more current when switching than quiescent, for which power noise can become problematic. In an ALU - where a lot of switching occurs - ECL can draw lower mean current than CMOS.

          Power supplies and logic levels
    The ECL circuits available on the open market usually operated with negative power supplies (-5.2 volts), and logic levels incompatible with other families. This meant that interoperation between ECL and other logic families, such as the popular TTL family, required additional interface circuits. The fact that the high and low logic levels are relatively close meant that ECL suffers from small noise margins, which can be troublesome.
    At least one manufacturer, IBM, made ECL circuits for use in the manufacturer's own products; the power supplies were substantially different from those used in the open market. [Read more]

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            Transistor–Transistor Logic (TTL)

    Transistor–Transistor Logic (TTL) is a class of digital circuits built from bipolar junction transistors (BJT), and resistors. It is called transistor–transistor logic because both the logic gating function (e.g., AND) and the amplifying function are performed by transistors (contrast this with RTL and DTL). It is notable for being a widespread integrated circuit (IC) family used in many applications such as computers, industrial controls, test equipment and instrumentation, consumer electronics, synthesizers, etc. Because of the wide use of this logic family, signal inputs and outputs of electronic equipment may be called "TTL" inputs or outputs, signifying compatibility with the voltage levels used.

      A real-time clock built of TTL chips designed about 1979.TTL logic was invented in 1961 by James L. Buie of TRW, "particularly suited to the newly developing integrated circuit design technology."[1]
    The first commercial integrated-circuit TTL devices were manufactured by Sylvania in 1963, called the Sylvania Universal High-Level Logic family (SUHL).[2] The Sylvania parts were used in the controls of the Phoenix missile. TTL became popular with electronic systems designers after Texas Instruments introduced the 5400 series with military temperature range in 1964 and the later 7400 series of ICs, specified over a lower range, in 1966.
    The Texas Instruments 7400 family became an industry standard. Compatible parts were made by Motorola, AMD, Fairchild, Intel, Intersil, Mullard, Siemens, Signetics, SGS-Thomson (STMicroelectronics Inc.), National Semiconductor and many other companies, even in the former Soviet Union. Not only did third parties make compatible TTL parts, but compatible parts were made using many other circuit technologies as well.
    The term "TTL" is applied to many successive generations of bipolar logic, with gradual improvements in speed and power consumption over about two decades. The last widely available family, 74AS/ALS Advanced Schottky, was introduced in 1985.[3] As of 2008, Texas Instruments continues to supply the more general-purpose chips in numerous obsolete technology families, albeit at increased prices. Typically, TTL logic chips integrate no more than a few hundred transistors. Functions within a single package generally range from a few logic gates to a microprocessor bit-slice. TTL also became important because its low cost made digital techniques economically practical for tasks previously done by analog methods.[4]
    The Kenbak-1, one of the first personal computers, used TTL for its CPU instead of a microprocessor chip, which was not available in 1971.[5] The 1973 Xerox Alto and 1981 Star workstations, which introduced the graphical user interface, used TTL circuits integrated at the level of ALUs and bitslices, respectively. Most computers used TTL-compatible logic between larger chips well into the 1990s. Until the advent of programmable logic, discrete bipolar logic was used to prototype and emulate microarchitectures under development.

    Standard TTL NAND, one of four in 7400TTL contrasts with the preceding resistor–transistor logic (RTL) and diode–transistor logic (DTL) generations by using transistors not only to amplify the output, but also to isolate the inputs. The p-n junction of a diode has considerable capacitance, so changing the logic level of an input connected to a diode, as in DTL, requires considerable time and energy.
    As shown in the top schematic at right, the fundamental concept of TTL is to isolate the inputs by using a common-base connection, and amplify the function using a common emitter connection. Note that the base of the output transistor is driven high only by the forward-biased base–collector junction of the input transistor. The second schematic adds to this a "totem-pole output". When V2 is off (output equals 1), the resistors turn V3 on and V4 off, resulting in a stronger 1 output. When V2 is on, it activates V4, driving 0 to the output. The diode forces the emitter of V3 to ~0.7 V, while R2, R4 are chosen to pull its base to a lower voltage, turning it off. By removing pull-up and pull-down transistors from the output stage, this allows the strength of the gate to be increased without proportionally affecting power consumption.[6][7]
    TTL is particularly well suited to integrated circuits because the inputs of a gate may all be integrated into a single base region to form a multiple-emitter transistor. Such a highly customized part might increase the cost of a circuit where each transistor is in a separate package. However, by combining several small on-chip components into one larger device, it reduces the cost of implementation on an IC.
    As with all bipolar logic, a small amount of current must be drawn from a TTL input to ensure proper logic levels. The total current drawn must be within the capacities of the preceding stage, which limits the number of nodes that can be connected (the fanout).
    All standardized common TTL circuits operate with a 5-volt power supply. A TTL input signal is defined as "low" when between 0 V and 0.8 V with respect to the ground terminal, and "high" when between 2.2 V and 5 V[8] (precise logic levels vary slightly between sub-types). Use of the TTL logic levels was so ubiquitous that complex circuit boards often contained chips made by many manufacturers in different logic families, selected based on availability and cost. Logic gates could often be treated as ideal Boolean devices without concern for harmful electrical incompatibilities.
    Like most integrated circuits of the period 1965�, TTL devices were usually packaged in through-hole, dual in-line packages with between 14 and 24 lead wires, usually made of epoxy plastic but also commonly ceramic. Beam-lead chips without packages were made for assembly into larger arrays as hybrid integrated circuits. Parts for military and aerospace applications were packaged in flat packs, a form of surface-mount package, with leads suitable for welding or soldering to printed circuit boards. Today, many TTL-compatible devices are available in surface-mounted packages.

          Comparison with other logic families
    Generally, TTL devices consume more power than an equivalent CMOS device at rest, but power consumption does not increase with clock speed as rapidly as for CMOS devices. Compared to contemporary ECL circuits, TTL uses less power and has easier design rules, but is typically slower. Designers can combine ECL and TTL devices in the same system to achieve best overall performance and economy. TTL was less sensitive to damage from electrostatic discharge than early CMOS devices.
    Due to the output structure of TTL devices, the output impedance is asymmetrical between the high and low state, making them unsuitable for driving transmission lines. This is usually solved by buffering the outputs with special line driver devices where signals need to be sent through cables. ECL, by virtue of its symmetric output structure, doesn't have this drawback.
    The typical "totem-pole" output structure often has a momentary overlap between the upper and lower transistors, resulting in a substantial pulse of current drawn from the supply. These pulses can couple in unexpected ways between multiple integrated circuit packages, resulting in reduced noise margin and lower performance. TTL systems usually have a decoupling capacitor for every one or two IC packages, so that a current pulse from one chip does not momentarily reduce the supply voltage to the others.
    Several manufacturers now supply CMOS logic equivalents with TTL compatible input and output levels, usually bearing part numbers similar to the equivalent TTL component and with the same pin-out diagrams. For example, the 74HCT00 series provides many drop-in replacements for bipolar 7400 series parts, but uses CMOS technology.

    Successive generations of technology produced compatible parts with improved power consumption, switching speed or both. Although vendors uniformly marketed these various product lines as TTL with Schottky diodes, some of the underlying circuits, such as used in the LS family, could rather be considered DTL.[9]
    Variations of and successors to the basic TTL family, which has a typical gate propagation delay of 10ns and a power dissipation of 10mW per gate, for a power-delay product (PDP) or switching energy of about 100 pJ, include:
        Low-power TTL (L), which traded switching speed (33ns) for a reduction in power consumption (1mW) (now essentially replaced by CMOS logic);
        High-speed TTL (H), with faster switching speed than standard TTL (6ns) but significantly higher power dissipation (22mW);
        Schottky TTL (S), introduced in 1969, which used Schottky diode clamps at gate inputs to prevent charge storage and speed switching time. These gates operated more quickly (3ns) but had higher power dissipation (19mW);
        Low-power Schottky TTL (LS) – used the higher resistance values of low-power TTL and the Schottky diodes to provide a good combination of speed (9.5ns) and reduced power consumption (2mW), and PDP of about 20 pJ. Probably the most common type of TTL since these were used as glue logic in microcomputers; essentially replacing the former H, L, and S sub-families.
        Fast (F) and Advanced-Schottky (AS) variants of LS from Fairchild and TI, respectively, circa 1985, with "Miller-killer" circuits to speed up the low-to-high transition. These families achieved PDPs of 10 pJ and 4 pJ, respectively, the lowest of all the TTL families.
    Most manufacturers offer commercial and extended temperature ranges; for example Texas Instruments 7400 series parts are rated from 0 to 70°C, and 5400 series devices over the military-specification temperature range of ?55 to +125°C.
    Radiation-hardened devices are offered for space applications
    Special quality levels and high-reliability parts are available for military and aerospace applications.
    Low-voltage TTL (LVTTL) for 3.3-volt power supplies and memory interfacing.
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              ========= PCIe serial =========
  Miscellelanous terms used with PCIe: pcie asynchronous, pcie rs-232, pcie rs-422, pcie rs-485, pcie serial, pcie serial board, pcie serial card, and pcie synchronous.
        ---- PCIe digital ----
  Miscellelanous terms used with PCIe:(pcie digital) pcie digital, pcie digital board, pcie digital card, pcie digital i/o, pcie digital input, pcie digital io, pcie lvds i/o, and pcie pecl i/o.
        ---- pcie opto-coupler
  Includes: pcie optically isolated, pcie opto, and pcie optoisolated.

              ========= PMC serial =========
  Miscellelanous terms used with PCIe: pmc asynchronous, pmc rs-232, pcie rs-422, pmc rs-485, pmc serial, pmc serial board, pmc serial card, and pmc synchronous.
        ---- PMC digital ----
  Miscellelanous terms used with PMC:(pcie digital) pcie digital, pcie digital board, pcie digital card, pcie digital i/o, pcie digital input, pcie digital io, pmc lvds i/o, and pmc pecl i/o.
        ---- PMC opto-coupler
Includes: pmc optically isolated, pmc opto, and pmc optoisolated.

              ========= PCI serial =========
  Miscellelanous terms used with PCI: pci asynchronous, pci rs-232, pci rs-422, pci rs-485, pci serial, pci serial board, pci serial card, and pci synchronous.
        ---- PCI digital ----
  Miscellelanous terms used with PCI:(pci digital) pci digital, pci digital board, pci digital card, pci digital i/o, pci digital input, pci digital io, pci lvds i/o, and pci pecl i/o.
        ---- PCI opto-coupler
Includes: pci optically isolated, pci opto, and pci optoisolated.

              ========= PC/104-Plus serial =========
  Miscellelanous terms used with PCIe: 104-plus asynchronous, 104-plus rs-232, 104-plus rs-422, 104-plus rs-485, 104-plus serial, 104-plus serial board, 104-plus serial card, and 104-plus synchronous.
        ---- PC/104-Plus digital ----
  Miscellelanous terms used with PC/104-Plus:(104-plus digital) 104-plus digital, 104-plus digital board, 104-plus digital card, 104-plus digital i/o, 104-plus digital input, 104-plus digital io, 104-plus lvds i/o, and 104-plus pecl i/o.
        ---- PC/104-Plus opto-coupler
Includes: 104-plus optically isolated, 104-plus opto, and 104-plus optoisolated.

              ========= cPCI serial =========
  Miscellelanous terms used with PCIe: cpci asynchronous, cpci rs-232, cpci rs-422, cpci rs-485, cpci serial, cpci serial board, cpci serial card, and cpci synchronous.
        ---- cPCI digital ----
Miscellelanous terms used with cPCI :(cpci digital) cpci digital, cpci digital board, cpci digital card, cpci digital i/o, cpci digital input, cpci digital io, pcie lvds i/o, and pcie pecl i/o.
        ---- cPCI opto-coupler
Includes: cpci optically isolated, cpci opto, and cpci optoisolated.

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