Analog I/O Boards
Analog I/O Boards

     General Standards Corporation is a leading supplier of a wide range of analog I/O boards for embedded applications on several form factors/busses,and for many operating systems.
        Features include:
        Up to 64 input channels per board;
        Programmable Sampling rates to 50M SPS;
        Multi-board synchronization;
        Sigma-Delta and Delta-Sigma Analog I/O;
        Resolutions from 12 bits to 24 bits.

    Form factors: PCI-Express, PMC, PC/104-Plus, PC/104-Express, VME, CCPMC, XMC, PCI, PCI-X, cPCI, and cPCI-X. View our large variety of PMC adapters

    Software drivers: Windows, Linux, VxWorks, MathWorks Simulink & xPC Target, Labview, QNX, etc.

    Free Windows, Linux, and Labview Drivers.
    Free loaner boards.

Selection Tables

        Analog Input Selection Tables: 24-Bit Delta-Sigma Analog In, 18-Bit Analog In, 16-Bit Analog In, 16-Bit Sigma-Delta In, 14-Bit Analog In, and 12-Bit Analog In.

        Analog Output Selection Tables: 18-Bit Analog Out and 16-Bit Analog Out.

        Analog I/O Selection Tables: 18-Bit Analog I/O, 16-Bit Analog I/O, and 12-Bit Analog I/O.

        In development: Analog I/O and Isolated Analog I/O.

Various I/O cables are available:
[View a list of cables, part numbers, and price]

To view our large variety of PMC adapters Click Here.

Free Drivers & Loaner Boards.
  New: Conduction Cooled PMC (CCPMC)

  Coming Soon: XMC and PC/104-Express

    Applications include: sonar, battery monitoring, voice digitizing, precision instrumentation, noise monitoring, and sona-buoys, etc.

For Info on Analog I/O Technology see:
        Setting Sample Rates
        Analog-to-digital Converter Technology
        ADC Structures/Types
        Sigma-Delta ADCs
        Applications of A/D Converters

            Setting Sample Rates

      PMC66-14HSAI4 Board
      The PMC66-14HSAI4 board's effective sampling rates are a function of the
register values of the four board parameters: Nvco, Nref, Ndiv-clk, and Ndec.
Please see section 3.4.3 of the 14HSAI4 manual for a detailed description of
how this works. The general problem is to find values for these parameters that
produce a solution to the equations in that section of the manual that yields the
user's desired sampling rate - or if it's not possible to get an exact solution - to
find a solution that minimizes the sampling rate error - so as to get as close as
possible to the user's desired sampling rate. A computer program was written
to allow users to quickly find the best solutions for any desired sampling rate
from 1.000 KHz to 50.000 MHz. The program is called 14HSAI4setup.

          Install the 14HSAI4setup Program
      Download "" from the GSC website to a computer running
Windows 2000 or later. Unzip the zip archive into any convenient location.
This will unzip into a new folder named "14HSAI4setup". Within that folder
will be an executable file named "14HSAI4setup.exe" and some support files
that are needed by the program. Just double-click the icon to run the program.
A shortcut that points to this program can be added to the desktop if desired.
There is no installation. This program may be removed from the computer by
just deleting the 14HSAI4setup folder, and any shortcuts to it you've created.
(A version of this program that works under Linux is available upon request.)

          To use this program:
      Enter the desired effective sampling frequency in Hertz - samples per second.
(e.g. 10.002 MHz would be entered as "10002000" - an integer without any
decimal point. Enter "0" to terminate the program.) The program will find a
solution, but will sometimes show multiple solutions. If several solutions are
shown note the Fsample(error) results and choose the best one from among
those listed.

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                Analog-to-digital Converter Technology

      The resolution of the converter indicates the number of discrete values it can produce over the range of analog values. The values are usually stored electronically in binary form, so the resolution is usually expressed in bits. In consequence, the number of discrete values available, or "levels", is usually a power of two. For example, an ADC with a resolution of 8 bits can encode an analog input to one in 256 different levels, since 28 = 256. The values can represent the ranges from 0 to 255 (i.e. unsigned integer) or from -128 to 127 (i.e. signed integer), for example, depending on the application.
    Resolution can also be defined electrically, and expressed in volts. The voltage resolution of an ADC is equal to its overall voltage measurement range divided by the number of discrete intervals as in the formula:
    In practice, the useful resolution of the converter is limited by the signal-to-noise ratio of the signal in question. If there is too much noise present in the analog input, it will be impossible to accurately resolve beyond a certain number of bits of resolution, the "effective number of bits" (ENOB). If a preamplifier has been used prior to A/D conversion, the noise introduced by the amplifier is an important contributing factor towards the overall SNR. While the ADC will produce a result, the result is not accurate, since its lower bits are simply measuring noise. The signal-to-noise ratio should be around 6 dB per bit of resolution required.

      An ADC has several sources of errors. Quantization error and (assuming the ADC is intended to be linear) non-linearity is intrinsic to any analog-to-digital conversion. There is also a so-called aperture error which is due to a clock jitter and is revealed when digitizing a time-variant signal (not a constant value).
      These errors are measured in a unit called the LSB, which is an abbreviation for least significant bit. In the above example of an eight-bit ADC, an error of one LSB is 1/256 of the full signal range, or about 0.4%.

      Important parameters for linearity are integral non-linearity (INL) and differential non-linearity (DNL). therefore you need to do a careful calculation when you do the convergence.

            Sampling rate
      The analog signal is continuous in time and it is necessary to convert this to a flow of digital values. It is therefore required to define the rate at which new digital values are sampled from the analog signal. The rate of new values is called the sampling rate or sampling frequency of the converter.
      A continuously varying bandlimited signal can be sampled (that is, the signal values at intervals of time T, the sampling time, are measured and stored) and then the original signal can be exactly reproduced from the discrete-time values by an interpolation formula. The accuracy is limited by quantization error. However, this faithful reproduction is only possible if the sampling rate is higher than twice the highest frequency of the signal. This is essentially what is embodied in the Shannon-Nyquist sampling theorem.
      Since a practical ADC cannot make an instantaneous conversion, the input value must necessarily be held constant during the time that the converter performs a conversion (called the conversion time). An input circuit called a sample and hold performs this task—in most cases by using a capacitor to store the analogue voltage at the input, and using an electronic switch or gate to disconnect the capacitor from the input. Many ADC integrated circuits include the sample and hold subsystem internally.


      All ADCs work by sampling their input at discrete intervals of time. Their output is therefore an incomplete picture of the behaviour of the input. There is no way of knowing, by looking at the output, what the input was doing between one sampling instant and the next. If the input is known to be changing slowly compared to the sampling rate, then it can be assumed that the value of the signal between two sample instants was somewhere between the two sampled values. If, however, the input signal is changing fast compared to the sample rate, then this assumption is not valid.
      If the digital values produced by the ADC are, at some later stage in the system, converted back to analog values by a digital to analog converter or DAC, it is desirable that the output of the DAC be a faithful representation of the original signal. If the input signal is changing much faster than the sample rate, then this will not be the case, and spurious signals called aliases will be produced at the output of the DAC. The frequency of the aliased signal is the difference between the signal frequency and the sampling rate. For example, a 2 kHz sinewave being sampled at 1.5 kHz would be reconstructed as a 500 Hz sinewave. This problem is called aliasing.
      To avoid aliasing, the input to an ADC must be low-pass filtered to remove frequencies above half the sampling rate. This filter is called an anti-aliasing filter, and is essential for a practical ADC system that is applied to analog signals with higher frequency content.
      Although aliasing in most systems is unwanted, it should also be noted that it can be exploited to provide simultaneous down-mixing of a band-limited high frequency signal (see frequency mixer).

      In A to D converters, performance can be improved using dither. This is a very small amount of random noise (white noise) which is added to the input before conversion. Its amplitude is set to be about half of the least significant bit. Its effect is to cause the state of the LSB to randomly oscillate between 0 and 1 in the presence of very low levels of input, rather than sticking at a fixed value. Rather than the signal simply getting cut off altogether at this low level (which is only being quantized to a resolution of 1 bit), it extends the effective range of signals that the A to D converter can convert, at the expense of a slight increase in noise - effectively the quantization error is diffused across a series of noise values which is far less objectionable than a hard cutoff. The result is an accurate representation of the signal over time. A suitable filter at the output of the system can thus recover this small signal variation.       An audio signal of very low level (with respect to the bit depth of the ADC) sampled without dither sounds extremely distorted and unpleasant. Without dither the low level always yields a '1' from the A to D. With dithering, the true level of the audio is still recorded as a series of values over time, rather than a series of separate bits at one instant in time.
      A virtually identical process, also called dither or dithering, is often used when quantizing photographic images to a fewer number of bits per pixel—the image becomes noisier but to the eye looks far more realistic than the quantized image, which otherwise becomes banded. This analogous process may help to visualize the effect of dither on an analogue audio signal that is converted to digital.
      Dithering is also used in integrating systems such as electricity meters. Since the values are added together, the dithering produces results that are more exact than the LSB of the analog-to-digital converter.
      Note that dither can only increase the resolution of a sampler, it cannot improve the linearity, and thus accuracy does not necessarily improve.

      Usually, signals are sampled at the minimum rate required, for economy, with the result that the quantization noise introduced is white noise spread over the whole pass band of the converter. If a signal is sampled at a rate much higher than the Nyquist frequency and then digitally filtered to limit it to the signal bandwidth then there are 3 main advantages:
      Digital filters can have better properties (sharper rolloff, phase) than analogue filters, so a sharper anti-aliasing filter can be realised and then the signal can be downsampled giving a better result a 20 bit ADC can be made to act as a 24 bit ADC with 256x oversampling the signal-to-noise ratio due to quantization noise will be higher than if the whole available band had been used. With this technique, it is possible to obtain an effective resolution larger than that provided by the converter alone. [Read more]

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                ADC Structures/Types

These are the most common ways of implementing an electronic ADC:

      1) A direct conversion ADC or flash ADC has a bank of comparators, each firing for their decoded voltage range. The comparator bank feeds a logic circuit that generates a code for each voltage range. Direct conversion is very fast, but usually has only 8 bits of resolution (255 comparators - since the number of comparators required is 2n - 1) or fewer, as it needs a large, expensive circuit. ADCs of this type have a large die size, a high input capacitance, and are prone to produce glitches on the output (by outputting an out-of-sequence code). Scaling to newer submicron technologies does not help as the device mismatch is the dominant design limitation. They are often used for video, wideband communications or other fast signals. A successive-approximation ADC uses a comparator to reject ranges of voltages, eventually settling on a final voltage range. Successive approximation works by constantly comparing the input voltage to the output of an internal digital to analog converter (DAC, fed by the current value of the approximation) until the best approximation is achieved. At each step in this process, a binary value of the approximation is stored in a successive approximation register (SAR). The SAR uses a reference voltage (which is the largest signal the ADC is to convert) for comparisons. For example if the input voltage is 60 V and the reference voltage is 100 V, in the 1st clock cycle, 60 V is compared to 50 V (the reference, divided by two. This is the voltage at the output of the internal DAC when the input is a '1' followed by zeros), and the voltage from the comparator is positive (or '1') (because 60 V is greater than 50 V). At this point the first binary digit (MSB) is set to a '1'. In the 2nd clock cycle the input voltage is compared to 75 V (being halfway between 100 and 50 V: This is the output of the internal DAC when its input is '11' followed by zeros) because 60 V is less than 75 V, the comparator output is now negative (or '0'). The second binary digit is therefore set to a '0'. In the 3rd clock cycle, the input voltage is compared with 62.5 V (halfway between 50 V and 75 V: This is the output of the internal DAC when its input is '101' followed by zeros). The output of the comparator is negative or '0' (because 60 V is less than 62.5 V) so the third binary digit is set to a 0. The fourth clock cycle similarly results in the fourth digit being a '1' (60 V is greater than 56.25 V, the DAC output for '1001' followed by zeros). The result of this would be in the binary form 1001. This is also called bit-weighting conversion, and is similar to a binary search. The analogue value is rounded to the nearest binary value below, meaning this converter type is mid-rise (see above). Because the approximations are successive (not simultaneous), the conversion takes one clock-cycle for each bit of resolution desired. The clock frequency must be equal to the sampling frequency multiplied by the number of bits of resolution desired. For example, to sample audio at 44.1 kHz with 32 bit resolution, a clock frequency of over 1.4 MHz would be required. ADCs of this type have good resolutions and quite wide ranges. They are more complex than some other designs.

      2) A ramp-compare ADC (also called integrating, dual-slope or multi-slope ADC) produces a saw-tooth signal that ramps up, then quickly falls to zero. When the ramp starts, a timer starts counting. When the ramp voltage matches the input, a comparator fires, and the timer's value is recorded. Timed ramp converters require the least number of transistors. The ramp time is sensitive to temperature because the circuit generating the ramp is often just some simple oscillator. There are two solutions: use a clocked counter driving a DAC and then use the comparator to preserve the counter's value, or calibrate the timed ramp. A special advantage of the ramp-compare system is that comparing a second signal just requires another comparator, and another register to store the voltage value. A very simple (non-linear) ramp-converter can be implemented with a microcontroller and one resistor and capacitor. Vice versa a filled capacitor can be taken from an integrator, time-to-amplitude converter, phase detector, sample and hold circuit, or peak and hold circuit and discharged. This has the advantage that a slow comparator cannot be disturbed by fast input changes.

      3) A delta-encoded ADC has an up-down counter that feeds a digital to analog converter (DAC). The input signal and the DAC both go to a comparator. The comparator controls the counter. The circuit uses negative feedback from the comparator to adjust the counter until the DAC's output is close enough to the input signal. The number is read from the counter. Delta converters have very wide ranges, and high resolution, but the conversion time is dependent on the input signal level, though it will always have a guaranteed worst-case. Delta converters are often very good choices to read real-world signals. Most signals from physical systems do not change abruptly. Some converters combine the delta and successive approximation approaches; this works especially well when high frequencies are known to be small in magnitude.

      4) A pipeline ADC (also called subranging quantizer) uses two or more steps of subranging. First, a coarse conversion is done. In a second step, the difference to the input signal is determined with a digital to analog converter (DAC). This difference is then converted finer, and the results are combined in a last step. This can be considered a refinement of the successive approximation ADC wherein the feedback reference signal consists of the interim conversion of a whole range of bits (for example, four bits) rather than just the next-most-significant bit. By combining the merits of the successive approximation and flash ADCs this type is fast, has a high resolution, and only requires a small die size.

      5) A Sigma-Delta ADC (also known as a Delta-Sigma ADC) oversamples the desired signal by a large factor and filters the desired signal band. Generally a smaller number of bits than required are converted using a Flash ADC after the Filter. The resulting signal, along with the error generated by the discrete levels of the Flash, is fed back and subtracted from the input to the filter. This negative feedback has the effect of noise shaping the error due to the Flash so that it does not appear in the desired signal frequencies. A digital filter (decimation filter) follows the ADC which reduces the sampling rate, filters off unwanted noise signal and increases the resolution of the output. (sigma-delta modulation, also called delta-sigma modulation)
Delay line ADC: Designed with delay lines.
[Read more]

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                Sigma-Delta ADCs

    Abstract: This in-depth article covers the theory behind a Delta-Sigma analog-to-digital converter (ADC). It specifically focuses on the difficult to understand key digital concepts of over-sampling, noise shaping, and decimation filtering. A description of new converter, the MAX1402, and several applications for Delta-Sigma converters are included.
    Sigma-delta converters offer high resolution, high integration, and low cost, making them a good ADC choice for applications such as process control and weighing scales. Designers often choose a classic SAR ADC instead, because they don't understand the sigma-delta types.
    The analog side of a sigma-delta converter (a 1-bit ADC) is very simple. The digital side, which is what makes the sigma-delta ADC inexpensive to produce, is more complex. It performs filtering and decimation. To understand how it works, you must become familiar with the concepts of oversampling, noise shaping, digital filtering, and decimation.
    This application note covers these topics.

    First, consider the frequency-domain transfer function of a traditional multi-bit ADC with a sine-wave input signal. This input is sampled at a frequency Fs. According to Nyquist theory, Fs must be at least twice the bandwidth of the input signal.     When observing the result of an FFT analysis on the digital output, we see a single tone and lots of random noise extending from DC to Fs/2 (Figure 1). Known as quantization noise, this effect results from the following consideration: the ADC input is a continuous signal with an infinite number of possible states, but the digital output is a discrete function whose number of different states is determined by the converter's resolution. So, the conversion from analog to digital loses some information and introduces some distortion into the signal. The magnitude of this error is random, with values up to ± LSB. [Read more]

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                Applications of A/D Converters

            Application to music recording
    ADCs are integral to current music reproduction technology. Since much music production is done on computers, when an analog recording is used, an ADC is needed to create the PCM data stream that goes onto a compact disc.     The current crop of AD converters utilized in music can sample at rates up to 192 kilohertz. Many people in the business consider this an overkill and pure marketing hype, due to the Nyquist-Shannon sampling theorem. Simply put, they say the analog waveform does not have enough information in it to necessitate such high sampling rates, and typical recording techniques for high-fidelity audio are usually sampled at either 44.1 kHz (the standard for CD) or 48 kHz (commonly used for radio/TV broadcast applications). However, this kind of bandwidth headroom allows the use of cheaper or faster anti-aliasing filters of less severe filtering slopes. The proponents of oversampling assert that such shallower anti-aliasing filters produce less deleterious effects on sound quality, exactly because of their gentler slopes. Others prefer entirely filterless AD conversion, arguing that aliasing is less detrimental to sound perception than pre-conversion brickwall filtering. Considerable literature exists on these matters, but commercial considerations often play a significant role. Most high-profile recording studios record in 24-bit/192-176.4 kHz PCM or in DSD formats, and then downsample or decimate the signal for Red-Book CD production.

            Other applications
    AD converters are used virtually everywhere where an analog signal has to be processed, stored, or transported in digital form. Fast video ADCs are used, for example, in TV tuner cards. Slow on-chip 8, 10, 12, or 16 bit ADCs are common in microcontrollers. Very fast ADCs are needed in digital oscilloscopes, and are crucial for new applications like software defined radio. ADC's dynamic range is also important. [Read more]

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Miscellelanous terms used with PCIe:
        ----- pcie analog ------- Includes: pcie analog, pcie analog board, pcie analog card, pcie analog i/o,
pcie analog input, and pcie analog io.
        ---- PCIe Data Acquisition -------
pcie data acquisition

Miscellelanous terms used with PMC:
        ----- PMC analog -------
Includes: pcie analog, pmc analog board, pmc analog card, pmc analog i/o,
pmc analog input, and pmc analog io.
        ---- PCIe Data Acquisition -------
pmc data acquisition

Miscellelanous terms used with PCI:
        ----- PCI analog -------
Includes: pcie analog, pci analog board, pci analog card, pci analog i/o,
pci analog input, and pci analog io.
        ---- PCI Data Acquisition -------
pci data acquisition

Miscellelanous terms used with PC/104-Plus:
        ----- PC/104-Plus analog -------
Includes: 104-plus analog, 104-plus analog board, 104-plus analog card, 104-plus analog i/o,
104-plus analog input, and 104-plus analog io.
        ---- PC/104-Plus Data Acquisition -------
104-plus data acquisition

Miscellelanous terms used with cPCI :
        ----- cPCI analog -------
Includes: pcie analog, cpci analog board, cpci analog card, cpci analog i/o,
cpci analog input, and cpci analog io.
        ---- cPCI Data Acquisition -------
cpci data acquisition

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